1. Field of the Invention
The present invention relates to a dynamic random access memory and the method for fabricating thereof, and in particular to a trench capacitor type dynamic random access memory and the method for fabricating thereof.
2. Description of the Background Art
In recent years, semiconductor devices having the capacity of higher level of integration and a large volume have been studied.
Among those semiconductor devices, in case of a dynamic random access memory (hereinafter, which is referred as a DRAM) consisted of a plurality of cells, which are constructed by MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and capacitors, many methods for miniaturizing the memory cell have been proposed in order to provide a semiconductor having the capacity of higher level of integration and a large volume.
One among the proposed methods for miniaturizing the memory cell is a DRAM cell having a general trench capacitor, which will be roughly described with reference to FIG. 1. FIG. 1 is a cross-sectional view of a DRAM cell fabricated according to a conventional art.
Referring to FIG. 1, a trench capacitor is constructed by a plate electrode 110, a capacitor dielectric layer 120, a charge storage electrode 130 and a strap 140. Generally, the depth of a trench is formed very deeply compared to the diameter of a semiconductor substrate 100.
A transistor has a drain electrode 220, a source electrode 230, a gate insulation layer 240 and a gate electrode 250, and is formed between the trench capacitors, which are adjoined with each other.
As described above, in the fabricating method according to the conventional art, a trench is formed very deeply compared with its diameter to secure the maximum capacitance in the same substrate area. That is, since capacitance of the capacitor is proportional to the area of a dielectric being formed between conductors, a trench has been formed deeply into the inside of the substrate in order to obtain the maximum capacitor area in a constant substrate area.
However, according to a semiconductor device having a capacity for higher level of integration, the deep to the diameter of the trench capacitor become increased more and more, as the result, a formation of a trench capacitor, that is, processes for forming a trench on a substrate and thereafter a dielectric layer and an electrode on the trench become very difficult, and the difficulty of the processes as described above results in reduction of the yield.
Accordingly, it is an object of the present invention to provide a DRAM in which a trench capacitor, which is more widen and shallow, is formed.
And, it is another object of the present invention to provide an align mark, which is adapted to use when fabricating a DRAM according to the present invention.
In order to achieve the above-described object of one aspect of the present invention, a dynamic random access memory having a trench capacitor, comprises: a first and a second silicon substrates which are interposed an insulation layer between thereof; a plurality of trench capacitors formed on the first silicon substrate; and transistors corresponding to the trench capacitors, respectively, formed on the second silicon substrate, in which the trench capacitors and the transistors are electrically connected with each other, respectively, by penetrating the insulation layer.
In order to achieve the above-described object of another aspect of the present invention, a method for fabricating a dynamic random access memory having a trench capacitor, comprises the steps of: forming a trench capacitor on the upper portion of a first semiconductor substrate doped with a first conductive type impurity; forming an insulation layer on the upper portion of the device body having the trench capacitor; attaching a second semiconductor substrate doped with a second conductive type impurity on the upper portion of the insulation layer; exposing a charge storage electrode of the trench capacitor by sequentially patterning the second semiconductor substrate and the insulation layer; forming a strap electrically connected with the charge storage electrode by filling a conductive material to the exposing portion, which is exposed by patterning the second semiconductor substrate and the insulation layer; removing a portion of the second semiconductor substrate and the strap and forming a device separating layer on the removed portion; and forming a transistor on the second semiconductor substrate, wherein a drain electrode of the transistor is electrically connected to the strap.
In order to achieve the above-described object of another aspect of the present invention, an alignment method when attaching the first and second semiconductor substrates comprises the steps of: forming an align key on the upper portion of the first semiconductor substrate; attaching the second semiconductor substrate to the upper portion of the first semiconductor substrate; exposing the align key on the first semiconductor substrate by etching the second semiconductor substrate; and aligning a transistor by the align key of the first semiconductor substrate when forming the transistor on the upper portion of the second semiconductor substrate.